The two new SoCs are the latest additions to Ambarella’s successful CVflow SoC family that offers automotive OEMs, tier-1s, and software development partners an open platform for differentiated, high-performance automotive systems.

ZF, a global technology tier-1 and supplier of systems for passenger cars and commercial vehicles, is working with Ambarella on viewing and sensing systems.

CV22FS and CV2FS SoC key features:

– CVflow architecture with DNN support

– Quad-core 1-GHz Arm® Cortex®-A53 with NEON DSP extensions and FPU

– Safety island with dual-core lock step (DCLS) Arm® R52 targeting ASIL-C

– Dense optical flow engine

– Dense stereo disparity engine (CV2FS only)

– ASIL B functional safety level

– High speed SLVS/MIPI CSI-2/LVCMOS interfaces

– Multi-channel ISP with up to 480-Megapixel/s input pixel rate

– Native support for RGGB, RCCB, RCCC, RGB-IR, and monochrome sensor formats

– Multi-exposure high dynamic range (HDR) processing and LED flicker mitigation

– Real-time hardware-accelerated fish-eye dewarping and lens distortion correction (LDC)

– 4-megapixel AVC encoding for video logging and wireless video streaming

– Rich set of interfaces includes CAN FD, Gigabit Ethernet, USB 2.0 host and device, dual SD card controllers with SDXC support, MIPI DSI/CSI-2 4-lane output

– Advanced security features, including OTP for secure boot, TrustZone®, and IO virtualization

– AEC-Q100 grade 2 (-40C to +125C (T_J) operating temperature)

– 10 nm process technology

Synopsys announced that NXP plans to deploy Synopsys’ native automotive design solutions to improve quality-of-results (QoR) and time-to-results (TTR) for its next-generation, safety-critical system-on-chip (SoC) designs. The accelerating evolution of vehicle technologies means that more automotive chips are required to satisfy higher automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS). To meet higher ASILs, functional safety mechanisms, such as triple-mode redundancy (TMR) and dual-core lock-step (DCLS), can be used. These mechanisms mitigate random hardware failures in automotive designs, such as single-event upsets (SEUs), but can present TTR, capacity, and QoR design challenges which can be significantly alleviated using Synopsys’ native automotive design solutions.

Using its 16-nanometer (nm) S32G274 automotive network processing chip, NXP tested Synopsys’ native solutions for implementing TMR registers. Compared to its existing flow, NXP observed significantly reduced IC Compiler II placement and legalization runtime by more than 20 percent. This functionality also markedly improved capacity of job execution, which enabled NXP to leverage the most cost-effective compute farm. In addition, the native automotive solutions alleviated routing congestion and wire length in dense areas of the design, and improved usability with simplified implementation and comprehensive reporting to replace NXP’s homegrown scripting solutions.

Synopsys’ native automotive solutions enable designers to achieve their target ASILs by providing the industry’s most comprehensive feature set to implement functional safety mechanisms, such as TMR, DCLS, and failsafe finite state machine (FSM). Synopsys’ native automotive solutions comprise a complete digital design flow incorporating functional safety (FuSa)-enabled technologies.

Level-4 and higher autonomous driving vehicles are required to adapt to the environment, to control the vehicle, and to conduct synchronized communications with the cloud. A wide range of technologies is necessary to develop these functions while maintaining high reliability and safety.

To address these challenges, Synopsys provides comprehensive automotive solutions:

• Synopsys virtual prototyping solutions provide early access to silicon chips and virtual ECUs, allowing software development and testing to start up to 12 months before hardware is available.
• Synopsys Fusion Design Platform provides the industry’s most comprehensive portfolio of foundry certified tools and flows. It enables full-flow optimization for concurrent clock and data (CCD), wire synthesis, and logic restructuring, delivering high performance while supporting low power consumption, small area and a high level of functional safety.
• Synopsys test solutions enable early validation of complex design-for-test (DFT) logic supported through full RTL integration while maintaining physical-, timing-, and power-awareness.
• The Synopsys Verification Continuum Platform natively integrates verification technologies, including virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping, debug and verification IP (VIP), to accelerate verification closure.
• Synopsys’ broad portfolio of silicon-proven DesignWare IP for automotive applications includes Interface IP, Logic Libraries, Embedded Memories, Data Converters, ARC Processors, Security IP and the Sensor and Control IP Subsystem. The ASIL Ready ISO 26262 certified IP portfolio with automotive safety packages accelerates SoC-level functional safety assessments to help designers reach target ASIL levels.